1. Field of the Invention
The present invention relates to a differential amplifier circuit for amplifying analog signals and more particularly, to an adaptively-biased differential amplifier circuit capable of linear behavior, which provides a superior transconductance linearity within a wide input voltage range and which is formed on a metal-oxide-semiconductor (MOS) integrated circuit device.
2. Description of the Prior Art
An adaptively-biased differential amplifier circuit for amplifying analog signals having superior transconductance linearity within a comparatively wide input voltage range is known as an "operational transconductance amplifier (OTA)". If the operational transconductance amplifier is comprised of MOS field-effect transistors (MOSFETs), it is termed an "MOS OTA".
With a source-coupled differential pair of first and second MOSFETs driven by a tail current, drain currents of the MOSFETs are expressed as follows.
Here, we assume that all the MOSFETs are operating in the saturation region, the characteristics of the MOSFETs are matched, and the channel-length modulation and the body effect can be ignored- Then, the drain currents I.sub.Di of the i-th MOSFETs are expressed by the following equations (1a) and (1b), where .beta. is the transconductance parameter, V.sub.GSi are the gate-to-source voltages of the i-th MOSFETs, and V.sub.TH is the threshold voltage thereof. EQU I.sub.Di =.beta.(V.sub.GSi -V.sub.Th).sup.2 (V.sub.GSi V.sub.Th)(1a) EQU I.sub.Di =O(V.sub.GSi V.sub.TH) (1b)
The transconductance parameter .beta. is expressed as EQU .beta.=(1/2)(W/L) .mu.C.sub.ox,
where .mu. is the effective surface carrier mobility, C.sub.ox is a gate-oxide capacity per unit area, and W and L are a gate width and a gate length of each MOSFET, respectively.
The equation (1a) is obtained by approximation to Schockley's equation.
If the tail current is defined as I.sub.sa and a differential input voltage is defined as V.sub.i, a differential output current .DELTA.I of the MOS differential pair is expressed as the following equations (2a) and (2b). ##EQU1##
The transconductance of the MOS differential pair is obtained by differentiating the equations (2a) and (2b) by the differential input voltage v.sub.i.
It is seen from the equation (2a) that the transconductance nonlinearity of the differential pair can be compensated perfectly if the tail current I.sub.ss has a square-law characteristic of the input voltage V.sub.i that satisfies the following relationship (3). ##EQU2##
When substituting the equation (3) into the equation (2a), the differential output current .DELTA.I is proportional to the input voltage V.sub.i, i.e, .DELTA.I=(2I.sub.0 .beta.)1/2.V.sub.i. Therefore, the transconductance becomes constant, i.e., d(.DELTA.I)/dV.sub.i =(2I.sub.0 .beta.).sup.1/2, within the input voltage range of .vertline.V.sub.i .vertline..ltoreq.(I.sub.ss /.beta.).sup.1/2.
FIG. 3 shows a functional block diagram of such adaptively-biased differential pair. In FIG. 3, a differential pair 1 is formed by two MOSFETs M1 and M2. Gates of the MOSFETs M1 and M2 are applied with the input voltage V.sub.i. A squaring circuit 2 for squaring the input voltage V.sub.i drives the differential pair 1 by its output current, i.e., the tail current I.sub.ss for the pair 1. The differential output current .DELTA.I of the differential pair is derived through an active load 3.
FIG. 4 shows the transconductance characteristics of the adaptively-biased differential pair and a differential pair with a constant tail current. As shown in FIG. 4, the transconductance linearity is compensated by the squaring circuit 2.
The conventional MOS OTA was first disclosed by A. Nedungadi and T. R. Viswanathan in IEEE TRANSACT IONS ON CIRCUITS AND SYSTEMS, Vol. CAS-31, No. 10, pp. 891-894, October 1984, entitled "Design of Linear CMOS transconductance Elements", which contains an unbalanced, source-coupled quad cell as a squaring circuit.
The circuit configuration of this conventional MOS OTA is shown in FIG. 1. In FIG. 1, N-channel MOSFETs M51, M52, M53 and M54 compose a cross-coupled quad cell. The pair of the MOSFETs M51 and M54 is driven by a constant current (current: (n+1)I) connected to the common-connected sources of the MOSFETs M51 and M54. The pair of the MOSFETs M52 and M53 is driven by another constant current sink (current: (n+1)I) connected to the common-connected sources of the MOSFETs M52 and M53. The transconductance parameters of the MOSFETs M51 and M52 are .beta. and those of the MOSFETs M53 and M54 are n.beta..
N-channel MOSFETs M56 and M57 whose sources are connected in common at a node B compose a differential pair, which is driven by a constant current sink (current: aI). The transconductance parameters of the MOSFETs M56 and M57 are .beta..
The drains of the MOSFETs M51 and M52 are connected in common at a node A to be connected to another constant current source (current: aI). An N-channel MOSFET M55 whose drain and gate are connected to one another is provided between the nodes A and B. The MOSFET M55 and the current sink disposed near the node A serves as a current level shifter for shifting the current level at the node A to that at the node B.
The gates of the MOSFETs M56, M53 and M51 are connected in common to be applied with a first input voltage V.sub.1. The gates of the MOSFETs M57, M54 and M52 are connected in common to be applied with a second input voltage V.sub.2.
P-channel MOSFETs M58 and M59 compose a current mirror circuit serving as an active load of the differential pair. An output current i is derived from the drain of the MOSFET M59.
The characters V.sup.+ and V.sup.- denote supply voltages, respectively.
An output current I.sub.L of the quad cell is expressed as the following equations (4a), (4b) and (4c). ##EQU3## where I.sub.D51 and I.sub.D52 are drain currents of the MOSFETs M51 and M52, respectively.
To make the bias current to the differential pair of MOSFETs M56 and M57 adaptive, the tail current I.sub.ss should be satisfy the following equation (5). ##EQU4##
Then, the transconductance g.sub.m of the conventional MOS OTA becomes constant within the input voltage range of EQU .vertline.V.sub.i .vertline..ltoreq.{(n+1)I/(n.beta.)}.sup.1/2, that is EQU g.sub.m ={(a-2n/(n+1)) (I/.beta.)}.sup.1/2
Since the coefficients of V.sub.i in the equation (5) need to be equal to each other, the following relationship (6) needs to be satisfied. ##EQU5##
Solving the relationship (6) for n provides the optimum value of n as ##EQU6##
Nedungadi et al disclosed the error characteristic of the transconductance linearity obtained by the SPICE simulation, where n=2, 2.1, 2.155, 2.2 and 2.3, as shown in FIG. 2. They described that the error was limited less than 0.1% in the case of n=2.155.
With the conventional MOS OTA of Nedungadi et al., to make the transconductance linear, one of the two MOSFETs forming each unbalanced pair needs to have a gate-width to the gate-length ratio (W/L) that is (1+2/3.sup.1/2) (.apprxeq.2.1547) times the ratio (W/L) Of the other thereof. However, such the ratio is extremely difficult to be fabricated on a large-scale semiconductor integrated circuit device (LSI), which means that this MOS OTA is impossible to be practically realized.
If the ratio of (1+2/3.sup.1/3) (.apprxeq.2.1547) is rounded or approximated to an integer, no satisfactory transconductance linearity can be obtained.
Also, an obtainable input voltage range for the perfect linear transconductance is very narrow. The circuit scale is large because unbalanced source-coupled pairs are employed.